library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity Automa is
port(
	Start: in std_logic;
	X2: out Std_logic;
	X1: out Std_logic;
	X0: out Std_logic;
	 CLK: in std_logic
);
end Automa;
architecture structural of Automa is
	signal state_reg_out: std_logic_vector(2 downto 0):=(others=>'0');
	signal state_reg_in: std_logic_vector(2 downto 0):=(others=>'0');
	begin
	-- istantio la funzione f
		fne_stato_prossimo: entity work.Automa_F
								  port map(
										Start=>Start, 
										prev_state=>state_reg_out,
										next_state=>state_reg_in
								  );
	-- registro di stato
		reg_stato: entity work.PIPO
					  generic map( dim=>3)
					  port map(
							data_in=>state_reg_in,
							data_out=>state_reg_out,
							CE=>'1',
							CLK=>CLK,
							Reset=>'0'
					  );
	-- istanzio la funzione g
		fne_uscita: entity work.Automa_G
						port map(
							X2=>X2,
							X1=>X1,
							X0=>X0,
							prev_state=>state_reg_out
						);
end structural;
